1. Field of the Invention
The present invention relates to a method and apparatus for carrying out connection and related input/output processing functions in a Synchronous Digital Hierarchy transport node (network).
2. Description of the Prior Art
In the design of a Synchronous Digital Hierarchy system, i.e. SDH or SONET, a problem is to carry out the correct functional scheme recommended in ITU-T G783 without adding too much complexity like it would happen with a straightforward interpretation of the recommendation.
The Recommendation ITU-T G783 is herewith incorporated by reference.
The key issue is typically the presence in the model of ‘connection functions’ (matrices) serving different layers (typically in a 4/3/1 system multiplex section layer, higher order path layer and lower order path layer) that in a general implementation should be connected to all the system inputs and outputs.
Other functional blocks, recommended by G783 as well, separate such connection functions, according to the model.
More particularly, the problem is how to connect input and output ports to the various matrices, inserting the correct signal processing and distributing in a suitable way the circuitry on a limited set of boards, without adding too much complexity.
A number of known approaches could be used for solving the above problem.                A possibility is simply abridging the model, making two or more connection functions collapse in only one and modifying the functional chain accordingly. The drawback of this approach is that some behaviours that are allowed by a strict standard implementation in this case are not possible (typically combination of protection schemes at different layers).        Another possibility is implementing the different connection functions (matrices) and the entire signal processing among them in (only) one physical board. The main drawbacks in this case are that on one side the system complexity is limited by the amount of circuitry that can be put on a single board, on the other side the cost of the system does not scale nicely with I/O ports but is concentrated in the common parts.        A third possibility consists in distributing the signal processing relative to functional blocks among matrices in different boards with respect to the connection functions. This implies either a high number of specialized boards (in addition with respect to the ‘ideal’ simplest architecture barely composed by input/outputs and matrices) or a very complex back-panel design with the signals going back and forward among such boards and the matrices.        